The present invention relates to a ferroelectric memory which stores information in accordance with a polarization state of a ferroelectric material interposed between electrodes of a capacitor.
A semiconductor memory using a ferroelectric material is a nonvolatile semiconductor memory storing and holding information in a polarization direction thereof. Conventional nonvolatile semiconductor memories using a ferroelectric material will be described below.
FIG. 4 shows the circuitry of a conventional semiconductor memory as disclosed in U.S. Pat. No. 4,873,664. FIGS. 5A, 5B, 5C, 5D, 5E, 5F and 5G show an operation timing of the conventional semiconductor memory of FIG. 4. FIG. 6 shows a hysteresis characteristic of a ferroelectric material used in a memory cell capacitor in the conventional semiconductor memory. FIG. 7 shows a hysteresis characteristic of a ferroelectric material used in a dummy cell capacitor in the conventional semiconductor memory.
In the circuitry of the conventional semiconductor memory of FIG. 4, a bit line (BIT) 26 and a complementary bit line (/BIT) 28 are connected with a sense amplifier 30. Memory cells 20a, 20b, and 20c and a dummy cell 46 are coupled to the bit line 26. Memory cells 20d, 20e and a dummy cell 36 are coupled to the complementary bit line 28. The memory cell 20a includes a MOS transistor 24 and a memory cell capacitor 22. The memory cell capacitor 22 includes two spaced apart plates, or electrodes, with a ferroelectric material between them. In the MOS transistor, the gate is connected with a word line 32, the drain is connected with the bit line 26, and the source is connected with a first electrode of the memory cell capacitor 22. A second electrode of the memory cell capacitor 22 is connected with a plate line 34. Similarly, the dummy cell 36 has a MOS transistor 38 and a dummy cell capacitor 40. The dummy cell capacitor 40 includes two spaced apart plates, or electrodes, with a ferroelectric material between them. The gate of the MOS transistor 38 is connected with a dummy word line 2, the drain is connected with the complementary bit line 28, and the source is connected with a first electrode of the dummy cell capacitor 40. A second electrode of the dummy cell capacitor 40 is connected with a dummy cell plate line 44. The sense amplifier 30 is activated by a sense signal SE.
The circuit operation of the circuit of the conventional nonvolatile semiconductor memory will be described below with reference to the operation timing shown in FIGS. 5A-5G, the hysteresis characteristic of the ferroelectric film of the memory cell capacitor shown in FIG. 6, and the hysteresis characteristic of the ferroelectric film of the dummy cell capacitor shown in FIG. 7.
FIGS. 6 and 7 show the hysteresis curves of the ferroelectric film. The abscissa represents the electric filed applied to the capacitor, and the ordinate represents the electric charge (polarization) corresponding to an electric field applied. Even when the electric field applied is zero, a polarization remains, that is, there exists a remanent polarization, in the ferroelectric capacitor, as shown in FIGS. 6 and 7 at points B, E, H, and K. The remanent polarization values are used to represent nonvolatile data to thereby achieve a nonvolatile semiconductor memory. When the data of the memory cell is "1", the memory cell capacitor has a state at point B of FIG. 6, whereas when the data is "0", the memory cell has a state at point E of FIG. 6.
Suppose that an initial state of the dummy cell capacitor is represented by the state at point K of FIG. 7. To read the data of the memory cell 20a, the logic voltages of the bit line 26, complementary bit line 28, word line 32, dummy word line 42, cell plate line 34, and dummy cell plate line 44 are each set to "L" (ground voltage: GND) as an initial state. Thereafter, the bit line 26 and the complementary bit line 28 are each set to a floating state. The logic voltage of the sense signal SE is set to "L" (ground voltage: GND).
Then, as shown in FIGS. 5A-5D, the word line 32, the dummy word line 42, the cell plate line 34, and the dummy cell plate line 44 are each set to a logic voltage "H". The logic voltage "H" of each of the word line 32 and the dummy word line 42 is a voltage (Vpp) obtained by boosting a supply voltage. The logic voltage "H" of each of the cell plate line 34 and the dummy cell plate line 44 is the supply voltage (Vcc). By this setting, the MOS transistor 24 of the memory cell 20a and the MOS transistor 38 of the dummy cell 36 are turned on. Thus, an electric field is applied to the memory cell capacitor 22 and the dummy cell capacitor 40. If the data of the memory cell 20a is "1" at this time, the memory cell 20a undergoes a state change from the state at point B of FIG. 6 to the state at point D. The difference Q1 between the electric charge at point B and the electric charge at point D is read as the voltage of the bit line 26. At this time, the dummy cell 36 undergoes a state change from the state at point K of FIG. 7 to the state at a point J. The difference Qd between the electric charge at point K and the electric charge at point J is read as the voltage of the complementary bit line 28. Then, the sense signal SE is set to the logic voltage "H" (supply voltage: Vcc). Thereby, the sense amplifier 30 amplifies the difference between the voltage of the bit line 26 derived from the memory cell 20a and the voltage of the complementary bit line 28 derived from the dummy cell 36. Then, the voltage of the bit line 26 is raised to the level of the supply voltage Vcc, and the voltage of the complementary bit line 28 is lowered to the level of the ground voltage GND, and data "1" of the memory cell 20a is read.
On the other hand, if the data stored in the memory cell 20a is "0", the memory cell 20a undergoes a state change from the state at point E of FIG. 7 to the state at point D. The difference Q0 between the electric charge at point E and the electric charge at point D is read as the voltage of the bit line 26. At the same time, the dummy cell 36 undergoes a state change from the state at point K of FIG. 7 to the state at point J. The difference Qd between the electric charge at point K and the electric charge at point J is read as the voltage of the complementary bit line 28. The sense amplifier 30 detects the difference between the voltage of the bit line 26 derived from the memory cell 20a and the voltage of the complementary bit line 28 derived from the dummy cell 36. Then, the sense amplifier drops the voltage of the bit line 26 to the level of the ground voltage GND, raises the voltage of the complementary bit line 28 to the level of supply voltage Vcc, and reads the data "0" of the memory cell 20a.
When the data of the memory cell 20a is "1", the amplifying operation of the sense amplifier 30 causes both the bit line 26 and the cell plate line 34 to have the supply voltage Vcc. Thereby, no electric field is applied to the memory cell capacitor 22, which then comes into the state at point E of FIG. 6. Thereafter, to restore the memory cell capacitor 22 to its original state at point B of FIG. 6, the voltage of the cell plate line 34 is set to the ground voltage to change the memory cell capacitor 22 from the state at point E of FIG. 6 to the state at point A, and then, the logic voltage of the word line 32 is set to "L". As a result, no electric field is applied to the memory cell capacitor 22. Thus, the memory cell capacitor 22 returns to the state at point B of FIG. 6. Thereby, rewriting of the data "1" to the memory cell 20a is completed. Normally, a boosted or raised voltage (Vpp) is supplied to the word line 32 so that the "H" voltage of the bit line 26 is sufficiently applied to the memory cell capacitor 22 when it is placed in the state at point A of FIG. 6.
On the other hand, when the data of the memory cell 20a is "0", the bit line 26 has the ground voltage and the cell plate line 34 has the supply voltage Vcc due to the amplifying operation of the sense amplifier 30. Therefore, the memory cell capacitor 22 has the state at point D of FIG. 6. Then, the logic voltage of the cell plate line 34 is set to "L", so that no electric field is applied to the memory cell capacitor 22. Thus, the memory cell capacitor 22 is changed from the state at point D of FIG. 6 to the state at point E. Then, the logic voltage of the word line 32 is set to "L". However, even at this time, no electric field is still applied to the memory cell capacitor 22. Thus, the memory cell capacitor 22 keeps the state at point E in FIG. 6. Thereby, rewriting of the data "0" to the memory cell 20a is completed.
When data of the memory cell 20a is "1", the complementary bit line 28 has the ground voltage, and the dummy cell plate line 44 has the supply voltage Vcc. Thus, the capacitor 40 of the dummy cell 36 has the state at point J of FIG. 7. Then, each of the dummy word line 42 and dummy cell plate line 44 is set to the ground voltage. Thus, no electric field is applied to the dummy cell capacitor 40. Thus, the dummy cell capacitor 40 returns from the state at point J to the state at point K of FIG. 7.
On the other hand, when the data of the memory cell 20a is "0", both the complementary bit line 28 and the dummy cell plate line 44 have the supply voltage Vcc. Thus, the dummy cell capacitor 40 has the state at point K of FIG. 7. Thereafter each of the dummy word line 42 and the dummy cell plate line 44 is set to the ground voltage, in which state no electric field is still applied to the dummy cell plate line 44. Thus, the dummy cell capacitor 40 keeps the state at point K of FIG. 7. In this manner, rewriting of the data "0" to the dummy cell 36 is completed.
FIG. 8 shows the circuitry of another conventional semiconductor memory in which the potential of a plate line is fixed (see, for example, Japanese Patent Application Laid-Open Nos. 2-110895 and 8-55484).
In the circuit of the semiconductor memory shown in FIG. 8, a sense amplifier 76 is connected with a bit line B and a complementary bit line /B. Memory cells MC1 and MC2 are connected with the bit line B and the complementary bit line /B, respectively. The memory cells MC1 and MC2 each have a MOS transistor T and a capacitor C. The capacitor C of the memory cell MC1 has two spaced-apart electrodes and a ferroelectric film between them. In the MOS transistor T of the memory cell MC1, its gate is connected with a word line W1, its drain is connected with the bit line B, and its source is connected with a first electrode of the associated capacitor C. A second electrode of the capacitor C is connected with a cell plate line P. Similarly, in the MOS transistor T of the memory cell MC2, its gate is connected with a word line W2, its drain is connected with the complementary bit line /B, and its source is connected with a first electrode of the associated capacitor C. A second electrode of the capacitor C of the memory cell MC2 is also connected with the cell plate line P. The sense amplifier 76 is activated by a sense signal SE.
This conventional semiconductor memory has a pre-charge circuit 70, an intermediate potential generation circuit 72, and a reference level generation circuit 74. According to a bit line pre-charge signal BLP, the pre-charge circuit 70 pre-charges the potentials of each of the bit line B and the complementary bit line /B to an intermediate level. The intermediate potential generation circuit 72 generates an intermediate potential between "H" and "L" levels of the bit line and supplies it to the plate line P and the pre-charge circuit 70. According to a bit line potential-setting signal BLST, the reference level generation circuit 74 sets the potentials of each of the bit line B and the complementary bit line /B to the ground potential level immediately before the potential of a word line (for example, W1) has a select level. Once the word line W1 has a select level, the reference level generation circuit 74 supplies a reference level to the bit line B and the complementary bit line /B on which information stored in a selected memory cell MC is read, by a dummy word line (DW1) that is placed at a select level synchronously with the word line (W1).
The read operation of this conventional nonvolatile ferroelectric memory is described below with reference also to waveform charts shown in FIGS. 9A, 9B, 9C, 9D, 9E, and 9F.
In a stand-by state, i.e., before access to the memory cell MC1 starts, the bit line B and the complementary bit line /B are pre-charged to an intermediate potential almost equal to the potential of the plate line P. Then, immediately before the potential of the word line W1 has the select level after the access starts, the bit line potential-setting signal BLST becomes active, and the bit line B and the complementary bit line /B are set to the ground potential (or supply potential). Thereafter, each of the word line W1 and the dummy word line DW1 has the select level, so that information stored in the selected memory cell MC is output to the bit line B while the reference level generation circuit 74 supplies the reference level to the complementary bit line /B. Thereafter, the sense amplifier 76 amplifies the differential potential between the bit line B and the complementary bit line /B and outputs it to the outside.
If the transistor T of the memory cell MC is placed in an off state and the first electrode (storage node) of the capacitor C is placed in a floating state in the above stand-by state, leak of an electric charge occurs between the storage node and a substrate although the amount of the leaked electric charge is slight. Therefore, the leak between the storage node and the substrate, which is normally at the ground potential level, results in drop of the potential of the storage node to a level in the vicinity of the ground potential level and inversion of a spontaneous polarization of the memory cell MC. Thus, in the conventional semiconductor memory, to prevent the inversion of the spontaneous polarization of the memory cell MC, the potential of the word line (W1 or the like) is set to a predetermined level between the select level and a non-select level to turn on the transistor T slightly. This is to allow the storage node to have an intermediate potential almost equal to the potential of the plate line P by, through the bit line B, compensating the storage node for an electric charge which has leaked to the substrate or the like.
The above two kinds of the conventional ferroelectric memories have the following problems.
First, in the first type of the conventional nonvolatile ferroelectric memory shown in FIG. 1, because the plate line is driven to have a predetermined potential for each access to a memory cell, a plate line-driving time is totally long. Accordingly, a high-speed operation cannot be accomplished and in addition, the power consumption is large due to repeated charge and discharge of the plate line.
The second type of the conventional ferroelectric memory shown in FIG. 8 does not have such a problem because a predetermined potential is always supplied to the plate line.
However, in the second conventional ferroelectric memory, to prevent the inversion of the spontaneous polarization of the ferroelectric film of the capacitor element in the memory cell MC, the word line (e.g. W1) is set to a predetermined level between the select level and the non-select level to slightly turn on the transistor T to thereby compensate, through the bit line B, the storage node for a leaked electric charge and hold the storage node at the potential substantially equal to the plate line during the stand-by mode, as described above. Accordingly, complicated control of the potential of the word line is required, and there is also a possibility that the transistor of the memory cell is not turned on owing to a variation in quality of component parts manufactured. In this case, the leak from the storage node cannot be compensated for and the spontaneous polarization will be inverted.